View ISL21007_717427.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL21007
Data Sheet April 12, 2007 FN6326.1
Precision, Low Noise FGATM Voltage References
The ISL21007 FGATM voltage references are extremely low power, high precision, and low noise voltage references fabricated on Intersil's proprietary Floating Gate Analog technology. The ISL21007 features very low noise (4VP-P for 0.1Hz to 10Hz) and very low operating current (150A, Max). In addition, the ISL21007 family features guaranteed initial accuracy as low as 0.5mV. This combination of high initial accuracy, low drift, and low output noise performance of the ISL21007 enables versatile high performance control and data acquisition applications with low power consumption.
Features
* Reference Output Voltage . . . . . . . . . . . . . . .1.25V, 2.50V * Initial Accuracy . . . . . . . . . . . . . . . . . . . . 0.5mV (B grade) * Input Voltage Range: . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V * Low Output Voltage Noise . . . . . . 4VP-P (0.1Hz to 10Hz) * Supply Current . . . . . . . . . . . . . . . . . . . . . . . .150A (Max) * Temperature Coefficient . . . . . . . . . . . . 3ppm/C (B grade) * Operating Temperature Range. . . . . . . . . -40C to +125C * Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC * Pb-Free Plus Anneal Available (RoHS Compliant)
Available Options
VOUT OPTION (V) 1.250 1.250 1.250 2.500 2.500 2.500 INITIAL ACCURACY (mV) 0.5 1.0 2.0 0.5 1.0 2.0 TEMPCO. (ppm/C) 3 5 10 3 5 10
Applications
* High Resolution A/Ds and D/As * Digital Meters * Bar Code Scanners * Basestations * Battery Management/Monitoring * Industrial/Instrumentation Equipment
PART NUMBER ISL21007BFB812Z ISL21007CFB812Z ISL21007DFB812Z ISL21007BFB825Z ISL21007CFB825Z ISL21007DFB825Z
Pinout
ISL21007 (8 LD SOIC) TOP VIEW GND or NC 1 VIN 2 DNC 3 GND 4 8 DNC 7 DNC 6 VOUT 5 TRIM
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL21007 Ordering Information
PART NUMBER (Note) ISL21007BFB812Z ISL21007CFB812Z ISL21007DFB812Z ISL21007BFB825Z ISL21007CFB825Z ISL21007DFB825Z PART MARKING 21007BF Z12 21007CF Z12 21007DF Z12 21007BF Z25 21007CF Z25 21007DF Z25 VOUT OPTION (V) 1.250 1.250 1.250 2.500 2.500 2.500 GRADE 0.5mV, 3ppm/C 1.0mV, 5ppm/C 2.0mV, 10ppm/C 0.5mV, 3ppm/C 1.0mV, 5ppm/C 2.0mV, 10ppm/C TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC PKG. DWG. # M8.15 M8.15 M8.15 M8.15 M8.15 M8.15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "-TK" suffix for tape and reel
2
FN6326.1 April 12, 2007
ISL21007 Pin Descriptions
PIN NUMBER 1 2 4 5 6 3, 7, 8 PIN NAME GND or NC VIN GND TRIM VOUT DNC Ground Connection Power Supply Input Connection Voltage Reference Output Connection Allows user trim 2.5% Do Not Connect; Internal Connection - Must Be Left Floating Do Not Connect; Internal Connection - Must Be Left Floating DESCRIPTION
Typical Application Circuit
1 +3V C1 10F 2 3 4 GND VIN NC GND NC NC VOUT NC 8 7 6 5
ISL21007-12, 25 SPI BUS X79000 1 2 3 4 5 6 7 8 9 10 SCK A0 A1 A2 SI SO /RDY UP DOWN OE /CS CLR VCC VH VL VREF VSS VOUT VBUF VFB 20 19 18 17 16 15 14 13 12 11 LOW NOISE DAC OUTPUT C1 0.001F
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC
3
FN6326.1 April 12, 2007
ISL21007
Absolute Voltage Ratings
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Max Voltage VIN to Gnd . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V Max Voltage VOUT to Gnd (10s). . . . . . . . . . . . . . . -0.5V to VOUT + 1 Voltage on "DNC" pins . . . . No connections permitted to these pins. Lead Temperature, soldering (10s) . . . . . . . . . . . . . . . . . . . . +260C ESD Rating Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600V Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Continuous Power Dissipation (TA = +70C) (Note 1) 8 Lead SOIC derate 5.88mW/C above +70C . . . . . . 471mW Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . .-40C to +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Common Electrical Specifications (ISL21007-12, -25)TA = -40C to +125C, unless otherwise specified.
PARAMETER VIN VOA DESCRIPTION Input Voltage Range VOUT Accuracy @ TA = +25C ISL21007B ISL21007C ISL21007D TC VOUT Output Voltage Temperature Coefficient (Note 2) ISL21007B ISL21007C ISL21007D IIN VOUT/t Supply Current Long Term Stability (Note 4) Trim Range tR Turn on Settling Time Ripple Rejection eN VN Output Voltage Noise Broadband Voltage Noise Noise Density VOUT = 0.1% f = 10kHz 0.1Hz f 10Hz 10Hz f 1kHz f = 1kHz TA = +25C 2.0 75 TBD 2.5 120 60 4 2.2 60 CONDITIONS MIN 2.7 -0.5 -1.0 -2.0 TYP MAX 5.5 +0.5 +1.0 +2.0 3 5 10 150 UNIT V mV mV mV ppm/C ppm/C ppm/C A ppm/1kHrs % s dB VP-P VRMS nV/Hz
Electrical Specifications (ISL21007-12, VOUT = 1.250V) VIN = 3.0V, TA = -40C to +125C, unless otherwise specified.
PARAMETER VOUT VOUT /VIN VOUT/IOUT DESCRIPTION Output Voltage Line Regulation Load Regulation 2.7V < VIN < 5.5V Sourcing: 0mA IOUT 7mA Sinking: -7mA IOUT 0mA ISC VOUT/TA Short Circuit Current Thermal Hysteresis (Note 3) TA = +25C, VOUT tied to GND TA = +165C CONDITIONS MIN TYP 1.250 100 10 20 40 50 700 100 150 MAX UNIT V V/V V/mA V/mA mA ppm
4
FN6326.1 April 12, 2007
ISL21007
Electrical Specifications (ISL21007-25, VOUT = 2.50V) VIN = 3.0V, TA = -40C to +125C, unless otherwise specified
PARAMETER VOUT VOUT /VIN VOUT/IOUT ISC VOUT/TA NOTES: 2. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40C to +125C = +165C. 3. Thermal Hysteresis is the change of VOUT measured @ TA = +25C after temperature cycling over a specified range, TA. VOUT is read initially at TA = +25C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25C. The difference between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For TA = +165C, the device under test is cycled from +25C to +125C to -40C to +25C. 4. FGA voltage reference long term drift is a logarithmic characteristic. Changes that occur after the first few hundred hours of operation are significantly smaller with time, asymptotically approaching zero beyond 1,000 hours. Because of this decreasing characteristics, long term drift is specified in ppm/1kHrs. DESCRIPTION Output Voltage Line Regulation Load Regulation 2.7V < VIN < 5.5V Sourcing: 0mA IOUT 5mA Sinking: -5mA IOUT 0mA Short Circuit Current Thermal Hysteresis (Note 3) TA = +25C, VOUT tied to GND TA = +165C CONDITIONS MIN TYP 2.500 50 10 20 50 50 200 100 150 MAX UNIT V V/V V/mA V/mA mA ppm
Typical Performance Curves (ISL21007-12) (REXT = 100k)
120 UNIT 3 100 80 IIN (A) 60 40 20 0 2.5 UNIT 1 IIN (A) UNIT 2 90 85 80 75 70 65 60 2.5 -40C +25C +125C 95
3.0
3.5
4.0
4.5
5.0
5.5
6.0
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
VIN (V)
FIGURE 2. IIN vs VIN (3 UNITS)
FIGURE 3. IIN vs VIN OVER TEMPERATURE
VOUT (V) (NORMALIZED TO 1.25V AT VIN = 3.0V)
1.25015 VO (V) (NORMALIZED TO VIN = 3.0V) 1.25010 UNIT 3 1.25005 1.25000 UNIT 2 1.24995 1.24990 UNIT 1 1.24985 1.24980 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5
150 100 50 0 -50 -100 -150 -200 -250 -300 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 +25C -40C +125C
FIGURE 4. LINE REGULATION (3 UNITS)
FIGURE 5. LINE REGULATION OVER TEMPERATURE
5
FN6326.1 April 12, 2007
ISL21007 Typical Performance Curves (ISL21007-12) (REXT = 100k)
0.15 +25C 0.10 0.05 VOUT (V) VOUT (mV) 0.00 -0.05 -0.10 -0.15 -7 -40C +125C 1.25005 1.25000 1.24995 1.24990 1.24985 1.24980 -6 -5 -4 SINKING -3 -2 -1 0 1 2 3 OUTPUT CURRENT (mA) 4567 SOURCING 1.24975 -40 UNIT 3 UNIT 2
(Continued)
1.25010 UNIT 1
-20
0
20 40 60 80 TEMPERATURE (C)
100
120
140
FIGURE 6. LOAD REGULATION OVER TEMPERATURE
FIGURE 7. VOUT vs TEMPERATURE (3 UNITS)
X: 5s/DIV Y: 500mV/DIV
X: 5s/DIV Y: 500mV/DIV
FIGURE 8. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FIGURE 9. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
X: 20s/DIV Y: 1V/DIV
120 1nF LOAD 100 80 ZOUT () VIN 60 40 10nF LOAD NO LOAD
VOUT = 1.25V (FOR TYP IIN)
20 0 1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 10. TURN ON TIME
FIGURE 11. ZOUT vs FREQUENCY
6
FN6326.1 April 12, 2007
ISL21007 Typical Performance Curves (ISL21007-12) (REXT = 100k)
GAIN IS x1000, NOISE IS 4Vp-p
(Continued)
NO OUTPUT CAPACITANCE X: 50s/DIV Y: 1V/DIV
+7mA
2mV/DIV
-7mA
FIGURE 12. VOUT NOISE, 0.1Hz to 10Hz
FIGURE 13. LOAD TRANSIENT RESPONSE
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k 1M 10nF LOAD 1nF LOAD VIN (DC) = 3V VIN (AC) = 50mVP-P NO LOAD
FREQUENCY (Hz)
FIGURE 14. PSRR vs CAPACITIVE LOADS
7
FN6326.1 April 12, 2007
ISL21007 Typical Performance Curves (ISL21007-25) (REXT = 100k)
120 UNIT 3 100 80 IIN (A) 60 40 20 0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 6.0 UNIT 1 UNIT 2 IIN (A) 100 95 90 85 80 75 70 65 60 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 +25C -40C +125C
FIGURE 15. IIN vs VIN (3 UNITS)
FIGURE 16. IIN vs VIN OVER TEMPERATURE
VOUT (V) (NORMALIZED TO 2.5V AT VIN = 3V)
2.50020 VO (V) (NORMALIZED TO VIN = 3.0V) 2.50010 2.50000 UNIT 2 2.49990 2.49980 2.49970 2.49960 2.5 UNIT 3 UNIT 1
100 50 0 -50 -100 -150 -200 -250 -300 -350 -400 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 6.0 -40C +25C +125C
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
FIGURE 17. LINE REGULATION (3 UNITS)
0.60 0.40 0.20 VOUT (mV) VOUT (V) 0.00 -0.20 -0.40 -0.60 -0.80 -1.00 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 +25C -40C +125C
FIGURE 18. LINE REGULATION OVER TEMPERATURE
2.5003 2.5002 2.5001 2.5000 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994 2.4993 -40 -20 0 UNIT 3 20 40 60 80 TEMPERATURE (C) 100 120 140 UNIT 1 UNIT 2 NORMALIZED TO +25C
SINKING
OUTPUT CURRENT (mA)
SOURCING
FIGURE 19. LOAD REGULATION OVER TEMPERATURE
FIGURE 20. VOUT vs TEMPERATURE (3 UNITS)
8
FN6326.1 April 12, 2007
ISL21007 Typical Performance Curves (ISL21007-25) (REXT = 100k)
(Continued)
X: 5s/DIV Y: 500mV/DIV
X: 5s/DIV Y: 500mV/DIV
FIGURE 21. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FIGURE 22. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
X: 20s/DIV Y: 1V/DIV
160 140 120 VIN ZOUT () 100 80 60 40 20 0 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 1nF LOAD NO LOAD
10nF LOAD
VOUT = 2.5V (FOR TYP IIN)
FIGURE 23. TURN ON TIME
FIGURE 24. ZOUT vs FREQUENCY
GAIN IS x1000, NOISE IS 4VP-P
NO OUTPUT CAPACITANCE X: 50s/DIV Y: 500mV/DIV
+5mA
2mV/DIV
-5mA
FIGURE 25. VOUT NOISE, 0.1Hz to 10Hz
FIGURE 26. LOAD TRANSIENT RESPONSE
9
FN6326.1 April 12, 2007
ISL21007 Typical Performance Curves (ISL21007-25) (REXT = 100k)
(Continued)
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k 1M 10nF LOAD 1nF LOAD VIN (DC) = 3V VIN (AC) = 50mVP-P NO LOAD
FREQUENCY (Hz)
FIGURE 27. PSRR vs CAPACITIVE LOADS
Applications Information
FGA Technology
The ISL21007 voltage reference uses floating gate technology to create references with very low drift and supply current. Essentially the charge stored on a floating gate cell is set precisely in manufacturing. The reference voltage output itself is a buffered version of the floating gate voltage. The resulting reference device has excellent characteristics which are unique in the industry: very low temperature drift, high initial accuracy, and almost zero supply current. Also, the reference voltage itself is not limited by voltage bandgaps or zener settings, so a wide range of reference voltages can be programmed (standard voltage settings are provided, but customer-specific voltages are available). The process used for these reference devices is a floating gate CMOS process, and the amplifier circuitry uses CMOS transistors for amplifier and output transistor circuitry. While providing excellent accuracy, there are limitations in output noise level and load regulation due to the MOS device characteristics. These limitations are addressed with circuit techniques discussed in other sections.
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting location should be reviewed. The device uses a plastic SOIC package which will subject the die to mild stresses when the PC board is heated and cooled and slightly changes shape. Placing the device in areas subject to slight twisting can cause degradation of the accuracy of the reference voltage due to these die stresses. It is normally best to place the device near the edge of a board, or the shortest side, as the axis of bending is most limited at that location. Mounting the device in a cutout also minimizes flex. Obviously mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy.
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 4VP-P. The noise measurement is made with a bandpass filter made of a 1 pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth. Noise in the 10kHz to 1MHz bandwidth is approximately 40VP-P with no capacitance on the output. This noise measurement is made with a 2 decade bandpass filter made of a 1 pole high-pass filter with a corner frequency at 1/10 of the center frequency and 1-pole low-pass filter with a corner frequency at 10 times the center frequency. Load capacitance up to 1000pF can be added but will result in only marginal improvements in output noise and transient response. The output stage of the ISL21007 is not designed to drive heavily capactive loads, so for load capacitances above 0.001F the noise reduction network shown in Figure 28 is recommended. This network reduces noise significantly over the full bandwidth. Noise is reduced to less than 20VP-P from 1Hz to 1MHz using this network with a 0.01F capacitor and a 2k resistor in series with a 10F capacitor. Also, transient response is improved with higher value output capacitor. The
Micropower Operation
The ISL21007 consumes extremely low supply current due to the proprietary FGA technology. Low noise performance is achieved using optimized biasing techniques. Supply current is typically 75A and noise is 4VP-P benefitting precision, low noise portable applications such as handheld meters and instruments. Data Converters in particular can utilized the ISL21007 as an external voltage reference. Low power DAC and ADC circuits will realize maximum resolution with lowest noise.
10
FN6326.1 April 12, 2007
ISL21007
0.01F value can be increased for better load transient response with little sacrifice in output stability.
VIN = 3.0V 10F 0.1F VIN VO ISL21007 GND 0.01F 10F 2k
FIGURE 28. HANDLING HIGH LOAD CAPACITANCE
Turn-On Time
The ISL21007 devices have low supply current and thus the time to bias up internal circuitry to final values will be longer than with higher power references. Normal turn-on time is typically 120s. This is shown in Figure 10. Circuit design must take this into account when looking at power up delays or sequencing.
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures, take the total variation, (VHIGH - VLOW), and divide by the temperature extremes of measurement (THIGH - TLOW). The result is divided by the nominal reference voltage (at T = +25C) and multiplied by 106 to yield ppm/C. This is the "Box" method for specifying temperature coefficient.
Output Voltage Adjustment
The output voltage can be adjusted up or down by 2.5% by placing a potentiometer from Vout to ground, and connecting the wiper to the TRIM pin. The TRIM input is high impedance, so no series resistance is needed. The resistor in the potentiometer should be a low tempco (<50ppm/C) and the resulting voltage divider should have very low tempco <5ppm/C. A digital potentiometer such as the ISL95810 provides a low tempco resistance and excellent resistor and tempco matching for trim applications.
11
FN6326.1 April 12, 2007
ISL21007 Typical Application Circuits
VIN = +5.0V R = 200 2N2905
VIN ISL21007 VOUT VOUT = 2.50V GND 2.5V/50mA 0.001F
FIGURE 29. PRECISION 2.5V 50mA REFERENCE
+2.7 to 5.5V 0.1F 10F
VIN VOUT ISL21007-25 VOUT = 2.50V GND
0.001F VCC RH + EL8178 - RL VOUT (BUFFERED) VOUT (UNBUFFERED)
X9119 SDA 2-WIRE BUS SCL VSS
FIGURE 30. 2.5V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
12
FN6326.1 April 12, 2007
ISL21007 Typical Application Circuits
10F 0.1F
+2.7 to 5.5V
VIN VOUT ISL21007-12 TRIM GND
2.5V 2.5%
VCC I2C BUS SDA SCL ISL95810 VSS
RH
RL
FIGURE 31. OUTPUT ADJUSTMENT USING THE TRIM PIN
+2.7 to 5.5V 0.1F 10F
VIN VOUT ISL21007-12 GND + -
EL8178 VOUT SENSE LOAD
FIGURE 32. KELVIN SENSED LOAD
13
FN6326.1 April 12, 2007
ISL21007 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6326.1 April 12, 2007

▲Up To Search▲

Price & Availability of ISL21007

	To Download ISL21007 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .